1. Technical Field
This invention relates to high temperature superconductive integrated circuits and, more particularly, to planar high temperature superconductive integrated circuits fabricated using ion implantation.
2. Discussion
High temperature superconductor (HTS) integrated circuits typically include a first HTS layer patterned and deposited on a substrate using photo-lithography. Unwanted portions of the first HTS layer are physically etched off using a variety of techniques, for example ion milling, reactive ion etching, plasma etching, and wet etching. An insulating dielectric layer is formed over the HTS layer. Then, a second HTS layer is patterned and deposited. Additional dielectric layers and HTS layers can be alternately formed on the second HTS layer.
To effectively grow the second HTS layer, the underlying dielectric layer has to be monocrystalline or highly oriented (in contrast to polycrystalline or amorphous). However, it is very difficult to grow the epitaxial dielectric layer on the patterned first HTS layer since a lattice match is required between the dielectric layer and two distinctly different surfaces, the substrate layer the first HTS layer. In addition to providing the lattice match, proper crystal growth must be maintained by an angled portion formed over edges of the first HTS layer.
Stress, thickness, uniformality and conformality of the dielectric layer must also be considered. A short circuit could occur between the first and second HTS layers through the dielectric layer near edges of the first layer. Furthermore, since the second HTS layer is deposited over the non-planar dielectric layer (primarily where the second HTS layer crosses over the first HTS layer), the second HTS layer could break, develop line discontinuity, and/or encounter significant reduction in supercurrent carrying ability (Jc) due to crystal orientation disruption and/or non-uniform crystal thickness (e.g. crystal too thin) near the edges of the first layer. The problems described above increase as additional dielectric and HTS layers are formed.
Therefore, a high temperature superconductive integrated circuit addressing the above-identified problems is desirable.
When the first HTS layer, the dielectric layer and the second HTS layer are deposited in separate steps, contact can be made between the first and second HTS layers through a contact hole in the dielectric layer. A top interface surface of first HTS layer is typically cleaned using chemical etching or ion-cleaning before the second HTS layer is patterned and deposited. Such cleaning can damage or alter the top interface surface of the first HTS layer and can create a thin non-superconducting layer resulting in decreased supercurrent carrying ability (Jc) or nonsuperconductivity.
A multi-layer planar high temperature superconducting integrated circuit formed on a substrate includes a first planar high temperature superconducting (HTS) layer deposited and patterned on the substrate and including a central region and two opposing regions abutting the central region. Ion implantation is used to destroy superconductivity in the opposing regions without interrupting the lattice structure of the opposing regions. A second planar HTS layer is deposited and patterned on the first HTS layer and includes a central region and two opposing regions abutting the central region. Ion implantation is used to destroy superconductivity in the opposing regions without interrupting the lattice structure of the opposing regions. A third planar HTS layer is deposited and patterned over the second HTS layer.
According to another embodiment of the invention, a multi-layer planar high temperature superconducting integrated circuit is formed on a substrate and includes a first planar high temperature superconducting (HTS) layer deposited and patterned on the substrate and including a central region and two opposing regions abutting the central region. Ion implantation at a first implant energy level is used to destroy superconductivity in the opposing regions without interrupting the lattice structure ion of the opposing regions. Ion implantation at a second energy level lower than the first implant energy level is used to destroy superconductivity of a top portion of the central region without destroying the lattice structure of the top portion and to define a contact. A second HTS layer is deposited and patterned over the first HTS layer and abuts the opposing regions of the first layer, the contact, and the top portion.
According to another embodiment of the invention, a planar high temperature superconducting integrated circuit is formed on a substrate and includes a first high temperature superconducting layer deposited and patterned on the substrate. The HTS layer includes a lower portion having opposing regions abutting a central region. The opposing regions have been bombarded using ion implantation with high-energy, deep-range ions to destroy superconductivity of the opposing region of the lower portion. A middle portion has opposing regions abutting a central region. The opposing regions have been bombarded using ion implantation with medium-energy, medium-range ions to destroy superconductivity of the opposing regions of the middle portion. An upper portion includes a central superconducting region.
Other objects, features and advantages will be readily apparent.